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Resumen General

The 43rd IEEE VLSI Test Symposium (VTS) will be held from April 28-30, 2025, in Tempe, AZ, USA. The symposium explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems, featuring keynotes, scientific paper presentations, industrial application paper presentations, special sessions, and Innovative Practices sessions.

Convocatoria

43rd IEEE VLSI Test Symposium 2025: Call for Contributions

The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems.

The symposium will take place on April 28-30, 2025, in Tempe, AZ, USA.

Topics of Interest

You are invited to participate and submit your contributions to VTS’25. The areas of interest include (but are not limited to) the following topics:

  • Generative AI Applications in Test and Security
  • Silicon Lifecycle Management
  • Silent Data Corruption
  • Test-Enabled Digital Twin
  • Analog – Mixed-Signal – RF Test
  • ATPG & Compression
  • Automotive Test & Safety
  • Built-In Self-Test (BIST)
  • Functional safety
  • Digital twin enabled test and security
  • High BW Test through High-Speed Interfaces
  • Testing for extreme environments
  • Test of Non-Si & Compound Circuits
  • Test and Security of Quantum Circuits
  • Test and Security of Photonic Circuits
  • Test and Security of Emerging Memory Technologies
  • Functional Debug through Scan
  • Fault Modeling and Simulation
  • Low-Power IC Test
  • Machine Learning for Test & Security
  • Microsystems/MEMS/Sensors Test
  • Memory Test and Repair
  • Test for 3D & Heterogeneous Integration
  • Yield Optimization
  • On-Line Test & Error Correction
  • Power & Thermal Issues in Test
  • System-on-Chip (SOC) Test
  • Test & Reliability of Biomedical Devices
  • Test & Reliability of High-Speed I/O
  • Test & Security of Machine Learning Hardware
  • Test Standards
  • FPGA Test
  • Defect-Based Test
  • Defect & Fault Tolerance
  • Delay & Performance Test
  • Design for Testability
  • Post-silicon Validation & Debug
  • Hardware Security
  • Embedded System & Board Test

Key Dates

  • Paper registration (title, abstract, and authors): November 25, 2024 (FIRM)
  • Paper PDF upload: December 2, 2024 (FIRM)
  • Notification of acceptance: February 8th, 2025
  • Special Session Proposals: January 31, 2025
  • Camera-ready upload: March 14th, 2025

Program Details

The program includes keynotes, scientific paper presentations, short industrial application paper presentations, special sessions, and Innovative Practices sessions.

Fechas Importantes

Fechas del Congreso

Conference Date

28 de abril de 202530 de abril de 2025

Envío

Paper registration (title, abstract, and authors)

25 de noviembre de 2024

Notificación

Notification of acceptance

8 de febrero de 2025

Versión Final

Camera-ready upload

14 de marzo de 2025

Otras Fechas

Paper PDF upload

2 de diciembre de 2024

Special Session Proposals

31 de enero de 2025

Clasificación de la Fuente

Fuente: CORE2023

Clasificación: TBR

Campo de Investigación: Computer Systems Engineering

Mapa

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